module   pcio2
title    'ISA (IBM-PC) Interface  Ver.2
          MOTOROLA INC.   14 February 1991'
  
          PCIO2      device    'P22V10';

"INPUTS"
    CLK            pin       1;        "ISA-Bus Clock "
    AEN            pin       9;        "Address Enable -- NOT DMA cycle"
    A14,A9,A8      pin       8,7,6;    "ADDRESS Bits14, 09-08"
    A7,A6,A5,A4    pin       5,4,3,2;  "ADDRESS Bits 07-04"
    IOR,IOW        pin      10,11;     "I/O Read*,I/O Write*"
    IRQA,IRQB      pin      13,23;

"OUTPUTS"
    MODA,MODB      pin       14,22;
    RESET          pin       21;       "Reset* latched"
    Q2,Q1,Q0       pin       20,19,18;
    HEN            pin       17;       "HOST ENABLE*"
    HRw            pin       16;       "HOST R/W*"
    Ben            pin       15;        "Buffer Enable for 74AC245"

    RESET               ISTYPE         'reg_D,Buffer';
    Q2,Q1,Q0            ISTYPE         'reg_D,Buffer';
    HRw                 ISTYPE         'reg_D,Buffer';

    High,Low       = 1,0;
    H,L,C,K,X      = 1,0,.C.,.K.,.X.;
    
    StateReset     = [RESET];
      Normal       = [ 1 ];
      SetReset     = [ 0 ];

    StateDir       = [ HRw ];          "Host Resd/WRITE*, buffer direction"
      ReadDir      = [ 1 ];
      WritDir      = [ 0 ];

    StateNo        = [ Q2..Q0 ];        
      Idle         = [ 0,0,0 ];
      S1           = [ 0,0,1 ];
      S2           = [ 0,1,0 ];
      S3           = [ 0,1,1 ];
      S4           = [ 1,0,0 ];
      S5           = [ 1,0,1 ];
      S6           = [ 1,1,0 ];
      S7           = [ 1,1,1 ];

    Rcyc   = !AEN & A9 & A8 & !A7 & A6 & !A5 & !A4 & !IOR;
    Wcyc   = !AEN & A9 & A8 & !A7 & A6 & !A5 & !A4 & !IOW;
    Addr   = [AEN,A14,A9,A8,A7,A6,A5,A4];

state_diagram StateReset
   state Normal:   if (Wcyc &  A14) THEN SetReset
                   ELSE                  Normal;
   state SetReset: if (Wcyc & !A14) THEN Normal
                   ELSE                  SetReset;

state_diagram StateDir
   state ReadDir:  if (!IOW) THEN WritDir
                   ELSE           ReadDir;
   state WritDir:  if (!IOR) THEN ReadDir
                   ELSE           WritDir;

state_diagram StateNo
   State Idle:     HEN = 1; Ben = 1;
                   if (!Rcyc & !Wcyc) THEN Idle   "stay put if not for me..."
                                      ELSE S1;
   State S1:       HEN = 1; Ben = 1;  goto S2;    "allow time to select the 74AC245 direction"
   State S2:       HEN = 1; Ben = 0;  goto S3;    "Now, enable the 74AC245 output"
   State S3:       HEN = 0; Ben = 0;              "assert HEN*"
                   if (Rcyc # Wcyc)   THEN S3     "...adn loop until the end of the I/O cycle"
                                      ELSE S4;
   State S4:       HEN = 1; Ben = 0;  goto Idle;  "deassert HEN*, and quit"
   State S5:       goto Idle;                     "these are dummies, just in case.."
   State S6:       goto Idle;
   State S7:       goto Idle;


equations
    [Q2,Q1,Q0].ck = CLK;
    RESET.ck      = CLK;
    HRw.ck        = CLK;

    MODA   =    !(RESET.Q & !IRQA);
    MODB   =      RESET.Q &  IRQB;


Test_vectors
   ([CLK,Addr,IOW,IOR,IRQA,IRQB] -> [HRw,RESET,MODA,MODB])
    [ C,^h34,0,1,0,1] -> [0,1,0,1];    "write to port, sets write dir."
    [ C,^h74,0,1,0,1] -> [0,0,1,0];    "write to  reset  address, asserts reset"
    [ C,^h34,1,0,0,1] -> [1,0,1,0];    "read from normal address, reset unchanged"
    [ C,^h34,0,1,0,1] -> [0,1,0,1];    "write to  normal address, deasserts reset"
    [ C,^h34,1,1,0,1] -> [0,1,0,1];
    [ C,^h34,1,1,1,1] -> [0,1,1,1];
    [ C,^h34,1,1,1,1] -> [0,1,1,1];

Test_vectors
   ([CLK,Addr,IOW,IOR] -> [HEN,Ben,HRw])
    [C,^h24,0,1] -> [1,1,0];           "this is NOT for me...., wrong addr"
    [C,^h34,1,1] -> [1,1,0];           "cycle starts, addresses valid...  "
    [C,^h34,1,1] -> [1,1,0];
    [C,^h34,1,0] -> [1,1,1];           "read cycle identified by IOR*     "
    [C,^h34,1,0] -> [1,0,1];
    [C,^h34,1,0] -> [0,0,1];
    [C,^h34,1,0] -> [0,0,1];
    [C,^h34,1,0] -> [0,0,1];
    [C,^h34,1,1] -> [1,0,1];
    [C,^h34,1,1] -> [1,1,1];
    [C,^h34,0,1] -> [1,1,0];
    
END pcio2