Name: ADPCMNS Type: Assembler Program Version: 1.0 Date Entered: 8/9/90 Last Change: 8/9/90 Description: Nonstandard CCITT ADPCM Speech Compression General Information: The file ADPCMNS.ASM contains the source code for the nonstandard implementation of the CCITT 32-kbit/s ADPCM speech coding algorithm on the DSP56001. Associated with this program is the file ADPCM.ASM which contains the source code for the standard version of the same algorithm. This help file contains usage notes for the nonstandard implementation. Refer to the help file ADPCM.ASM for usage notes on the standard implemen- tation. Complete documentation for both versions can be found in the Motorola application report "Full-Duplex 32-kbit/s CCITT ADPCM Speech Coding on the Motorola DSP56001" available as document APR9/D from the Motorola Literature Distribution Center. The program ADPCMNS.ASM implements the algorithm defined in CCITT Recommendation G.721: "32 kbit/s Adaptive Differential Pulse Code Modulation" dated August 1986. This version of the implementation does not adhere to the complete specification. It does provide a more direct and efficient implementation of algorithm and produces comparable quality to the standard version. The source code in ADPCMNS.ASM contains the necessary code for a real- time I/O interface. The details of this interface are described below. As with the standard version the I/O interface can easily be modified for other configurations. This code has been tested with a real-time hardware platform and is believed to have overall output quality similar to the standard code. Exhaustive tests have not been performed, however, so the actual performance under all conditions can not be assured in all cases. It is the responsibility of the user to verify correct operation. Usage Notes: The source code in the file ADPCMNS.ASM is set up to run the ADPCM algorithm in a real-time, full-duplex mode. The I/O interface of the code was chosen primarily for a convenient hardware test platform. A diagram is shown below. The test setup basically consists of two DSP56000ADS systems connected to a codec interface board. This board has two Motorola MC145503 codecs that provide the PCM interface. Each ADS board is connected to one of the MC145503 codecs via the J5 or J3 connectors which connect to the SSI port of the DSP56001. A simplified diagram of this interface is shown below. Complete details of the codec circuit can be found in the MC145503 data sheet. Many other codecs have a very similar interface to the DSP56001 SSI port. Eight port B general purpose I/O pins are used for the ADPCM link. Pins PB0 through PB3 are used as outputs and pins PB4 though PB7 are used as inputs. These pins are connected between the two ADS boards by connecting the appropriate lines on the 96-pin J3 connector on the ADS boards. The clocks for the two codecs are provided by a common clock source on the codec board. Each ADS board synchronizes the input and output based on the SSI port. Since the SSI interfaces on both boards are derived from a common clock, the entire system is synchronized. The initialization of the SSI port is done in the INIT routine. The SSI is set for synchronous, normal mode with 8 bit words, continuous exter- nal clock, and word length external frame sync. The I/O is synchronized by polling the SSI receive data register full flag (RDF), bit 7 in the SSI status register. When this flag is set, the program reads in the new PCM word for the ADPCM encoder, and outputs the ADPCM decoder output for the next SSI transmit slot. The encoder outputs the four bit ADPCM value to port B pins PB0 through PB3 by writing to the port B data register (PBD). The decoder reads in the encoded ADPCM word from port B pins PB4 through PB7 by reading the PBD register. CODEC 1 ADS 1 -------- ----------- Analog In | | | | ADPCM Channel ------>| | PCM | PB4.7|/-----------+ | |/---------\|SSI |\---------+ | Analog Out| |\---------/| | | | <------| | Channel | PB0.3|-------+ | | | | | |-----+ | | | -------- ----------- | | | | ^ | | | | | | | | | Clock ------+ | | | | | | | | | v | | | | -------- ----------- | | | | Analog In | | | |/----+ | | | ------>| | PCM | PB4.7|\------+ | | | |/---------\|SSI | | | Analog Out| |\---------/| |----------+ | <------| | Channel | PB0.3|------------+ | | | | ADPCM Channel -------- ----------- CODEC 2 ADS 2 Block diagram of real-time test platform 2.048 MHz | | 8 kHz MC145503 | | DSP56001 -------- | | ---------- | RDC |<--- | | | | | | | | | | PB0|-----> Analog In | TDC |<---+-----+--------->|SCK . | . ------>| | | | . | . | RDE |<--- | | PB3|-----> Analog Out| | | | | | <------| TDE |<---+---------+----->|SC2 PB4|<----- | | | . | . | RDD |<--------------------|STD . | . | | | PB7|<----- | TDD |-------------------->|SRD | -------- ---------- DSP56001/MC145503 Interface Although the CCITT defines the ADPCM specification for conversion of PCM data to encoded ADPCM data, the algorithm itself operates on linear input data. This code has also been tested with 16-bit linear data from 16-bit A/D's and D/A's. In this case the PCM conversion routines EXPAND and COMPRESS were removed. The output data required a two bit left shift since this shift was included in the COMPRESS routine. Memory Usage: Program Data Internal 479 70 (X) 72 (Y) External 132 -------- --- --- Total 611 142 The program uses only internal X and Y memory so no external data memory is required. Most of the 132 words of external program memory that is required is taken up by the INIT routine and the load-time constant table storage. The remaining words are part of the COMPRESS routine. Most applications will not require simultaneous use of both mu-law and A-law compression. If either the mu-law or A-law portion of the COMPRESS routine is removed then the entire run-time portion of the nonstandard code will reside in internal memory. If a host processor is attached to the DSP56001 then no external memory will be required. Otherwise, slower memories can be used during the initialization process. Performance Summary: The following shows the order of execution of the routines and the worst case processing time (in instruction cycles) for each routine. A routine defined as the code between commented sections even though some processing for that function may not be included in this code. Note that an instruc- tion cycle is defined as two clock cycles on the DSP56001. Encoder Decoder FMULT (x8) FMULT (x8) ACCUM 14 ACCUM 14 LIMA 4 LIMA 4 MIX 9 MIX 9 EXPAND 14 RECONST 10 SUBTA 2 ADDA 1 LOG 28 ANTILOG 28 SUBTB 1 TRANS 32 QUAN 41 ADDB 6 RECONST 10 ADDC 11 ADDA 1 XOR ANTILOG 28 UPB (x8) 72 TRANS 32 UPA2 25 ADDB 6 LIMC 5 ADDC 11 UPA1 14 XOR LIMD 8 UPB (x8) 72 FLOATA 7 UPA2 25 FLOATB 1 LIMC 5 TONE 3 UPA1 14 TRIGB 15 LIMD 8 FUNCTF 5 FLOATA 7 FILTA 4 FLOATB 1 FILTB 3 TONE 3 SUBTC 11 TRIGB 15 FILTC 3 FUNCTF 5 TRIGA 3 FILTA 4 FUNCTW 5 FILTB 3 FILTD 4 SUBTC 11 LIMB 7 FILTC 3 FILTE 4 TRIGA 3 COMPRESS 39 FUNCTW 5 EXPAND FILTD 4 SUBTA LIMB 7 LOG FILTE 4 SUBTB misc. 116 SYNC misc. 117 ------------------- ------------------- TOTAL 513 Icycles TOTAL 471 Icycles